OBE Assignment (BITS 1. FTMK BITI S1. G1: Topic 3 subtopic 4: PC relative addressing. It usually used in conditional branches. PC in PC- relative addressing mode bring a meaning of . The offset is the number of instructions forward or backward that must be skipped to get to the instruction labeled Label. The offset value can be an interpreted label value or immediate value. PC- relative addressing occurs in branch instructions, such as beq and bne. These instructions are I- type instructions, with the following format. It makes sense to jump relative to the PC, because the instruction we jumped from must have been the one at PC. For example, if you had a branch instruction at address 1. PC relative addressing in action. Below diagram shows how an effective address is generated when using PC relative addressing mode. SOON BOON JIANB0. Variations over instructions and addressing modes. SECTION 5: VARIATIONS OVER INSTRUCTIONS. AND ADDRESSING MODES 5. SUPPLEMENTARY CHAPTER 2 INSTRUCTION ADDRESSING MODES 663. If all of a program’s memory referencing instructions will be specified as dis-. You might be interested in noticing that relative addressingis similar to base. Addressing modes in assembly language programming. One approach for making programs relocatable is program counter relative addressing. IJMP, ICALL – Indirect program memory addressing. Addressing Modes RJMP, RCALL – Relative program memory addressing. Arithmetic Instructions. Jump and Call Instructions. 5.6 RELATIVE ADDRESSING MODES. Program-relative addressing's most important thing is that we can get programs which are independent of its location. Main Memory AM: Addressing Mode OF: Operation Field BR. Program Memory Relative addressing Program Memory Indirect addressing. Microprocessors Wisam I Hasan 22 Program Direct Addressing Store the address with the op-code JMP 10000 5 bytes instructions (op. Summary of Addressing Modes in MIPS. PC-Relative Addressing This is used in the beq and bne. CISC ISAs are meant to minimize the amount of memory used for a program by providing a large number of instructions.
RELATIVE. ADDRESSING MODES. Usually, with relative addressing CPU interprets AF's content like a shifting. RA, so that EA=(AF)+RA. Let's see four of the most used. RA. But, what. is PC's content exactly when instruction is running? In section 5. 3 we. Like PC-relative addressing. The PC-relative addressing mode can be used to load a register with a value stored in program memory a short distance away from the current instruction. Simplez and Simplez+i. But there is other (especially in RISCs, like Registrez. RA is present instruction's address. But, we study these. Usually, a jump instruction points out a. AF field. But data could. MM, and then we need another addressing mode. If we want to be able to branch. AF's most significative bit is a sign bit (figure 5. Actually, what instruction. AF field) is relative shifting over this instruction's location. MM's place. We will get back over this with an example at section 6. An AM's bit shows if instructions refer an instruction. Now it isn't used very. So we should see a little illustrative example. Addresses have sixteen bits, they're compounded between 0 and D'6. H'FFFF. If with OF and AM field we fill. AF, so we could address directly 2. B. A solution off. We consider MM structured in 2. B every one. If we. D'2. 55=H'FF). Effective address (when P=1) is obtained. AF's bits (eight in the example) and the most significative. PC's register bits. In load time we can locate him in any other page and. It's too independent of its location, in sense we. If it doesn't. go in a page, or if we want to set data in a different page, we should. If we use BR like base register, effective address is. EA=(AF)+(BR). It seems that there aren't differences with indexed addressing. The. difference is in the use we give to these modes. An index register's function is to contain an index that is changing. On the contrary, with base- relative addressing. This register's function. Which is. added to AF in running time. It's enough. including at the beginning necessary instructions to load in a base register. B since where it's really loaded (figure 5. Sometimes this mode is only used to access data zone, and program- relative. The idea is that operative system fixes base address. Program, in this case isn't independent of its location: if we consider. But it is well relocatable. In this kind of. CPUs its frequent that every base register has a. So, operative system can assign MM zones to every. Figure 5. 1. 0 represents. CPU has now segment registers. When accessing Main Memory. MM), segment registers acts as base registers. If the segment register content shifts. EA ( Effective Address) (see figure. EA has 2. 0 bits, so we can address an 1 Mb memory. We can say. that each one of these registers defines a segment in MM with a 6. Though this can. occur, normally segments don't have maximum length (6. Kb in this example). Of course, segment registers can have. Shown instructions are 3- byte. AF. Instruction (I1) accesses a datum of relative. H. For example, in an instruction. Indexing and PC- relative addressing modes, EA is. EA = ((AF) + (PC)) + (IR) EA. Effective Address. AF = Address Field. PC = Program Counter. IR = Index Register. If there is a base register ( or offset register ) for code ( CBR ) or. DBR ), effective address if we apply post- Indexing address mode. EA = ((AF) + (CBR)) + (DBR) + (RI). DYNAMIC. REALLOCATION. In chapter 4. 6 we explained the need for joining relative. MM. ( Main Memory ) addresses for making the program reallocated. These. joints can be made by software ( a reallocator loader. We saw that PC- relative addressing mode ( and with other limitations. PC) we are obtaining the real. MM. Base address is determined when the program is running ( the. This is the concept of dynamic. This is so because ( as we saw in chapter 5. If the memory amount in the computer is little, the suspended. And. when the operating system is going to activate it another time, it has. PM. But in that time interval is very possible that other. MM was changed. and the load of our program has to be in a different part of MM of the. Indeed, a reallocator loader can adjust. But there is a. problem when a reference is made using a pointer. Normally, program loads. An example can clarify the former paragraph. Some time later it decides to load the program again. A first problem (with simple solution) is that there. Supposing this, the loader adjusts DF. In this example. if it is used a base register, BR, the loader has no need to adjust anything. When the program is. BR, and. this value adds to the offset in every access. MM. Those registers. R3. 1 is a special case: is the program counter. We will see that this functional characteristic. Those addresses can be in one of the registers or in four bytes in. MM. In any case, all operands stored in MM are addressed by their. Little endian agreement; figure 5. Their first byte is dedicated. Each of them has at least one byte in which the first three. If the operand. is in the MM, then follows four bytes, which corresponds with the addressing. AF. Applet. In figure 5. With the three bits of the AM field we code the addressing. In autoincrement and. However, in indirect. Ri) in this case is not the effective. MM in which it is the effective address, always. Increments the (PC) in 2 units. CLR. B . 0. 00. 00. Clear the 8 less significant bits of R0. Increments the (PC) in 2 units. CLR. L . Increments (PC). CLR . Increments (R0). Increments the (PC) in 2 units. MOVE. B . 0 , . 1. Moves the 8 less significants bits of R0 to the same bits of R1. Increments. the (PC) in 3 units. MOVE . First, decrements (R6); the result is. I. e., dl is the content of four bytes at MM, and. Increments the (PC) in 6 units. ADD. B . 7 , #2. 55. As . Adds (bytes) (R7). R3. 1)) = 2. 55, storing the result in R7 (it affects only to the lower. As AM2 = 0. 10 (autoincrement), then increments (R3. PC), in one. unit (because we have ADD. B), in order to address the next instruction. Example instructions for the example in the text. Because we have instructions of variable length, the CU must properly. What it happens is that the program counter, R3. In this case, as PC=R3. The immediate addressing mode is obtained using Ri=R3. PC with autoincrement. EA=(Ri)=(PC). In fact, when the opcode and the addressing. CPU will increment the. PC properly so it usually can point to the first byte of the next instruction. We invite the reader to think about similar cases in order to. The absolute addressing mode results doing Ri=R3. PC with indirect autoincrement. EA=((Ri))=((PC)).
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